Electrostatic discharge and electrical overstress account for more than fifty (50) percent of the field related failures in integrated circuits. In particular, electrostatic discharge (ESD) and electrical overstress (EOS) protection circuitry plays an important role in the design, layout and testing of integrated circuits (IC) because many of the functional circuit elements on state-of-the-art integrated circuits are susceptible to high voltages caused by, among other things, electrostatic build-up of charge. This is especially true for complementary metal oxide semiconductor (CMOS) based integrated circuits because in high density CMOS circuits, high voltages caused by electrostatic build-up can destroy gate oxides associated with individual transistors and logic gates, etc. To protect against these types of failures, many attempts have been made to develop ESD and EOS protection devices.
One such attempt is disclosed in U.S. Pat. No. 4,692,781 to Rountree et al. entitled Semiconductor Device with Electrostatic Discharge Protection, assigned to Texas Instruments, Inc. The '781 patent discloses an input protection circuit containing a thick-oxide transistor connected between a metal I/O pad and ground. The spacing between the metal-to-silicon drain contact and the channel of this transistor is made large so that the metal drain contact will not be melted by heat propagated along the silicon surface during a current spike caused by an ESD event. U.S. Pat. No. 4,952,994 to Lin entitled Input Protection Arrangement for VLSI Integrated Circuit Devices, assigned to Digital Equipment Corp., also discloses an input protection circuit for diverting electrostatic discharge current away from functional circuit elements which are connected to I/O pads on an integrated circuit chip. The input protection circuit comprises a MOS transistor having a gate electrode and a field oxide insulating layer capable of sustaining high voltages. Other attempts to develop ESD/EOS protection circuits are also disclosed in U.S. Pat. Nos. 5,404,041, 5,450,267 and 5,468,667 to C. H. Diaz, C. Duvvury and S. M. Kang. In particular, the '041 and '667 patents disclose MOS-type ESD/EOS protection devices with source and drain contact spacings that are designed to increase the failure threshold of the protection devices. In addition, the '267 patent discloses an ESD/EOS protection circuit including both MOS and bipolar transistors.
FIG. 1 also illustrates a conventional NMOS-based ESD device having a comb-shaped drain electrode 10 connected to an input/output pad, a comb-shaped source electrode 14 connected to a reference signal line (VSS) and a comb-shaped gate electrode directly coupled to the comb-shaped source electrode 14 by vias, as illustrated. Direct electrical contact is also made between the source electrode 14 and the P-well in which the NMOS transistor is formed by a pair of fingers which contact P+ contact regions in the P-well using a plurality of vias. Unfortunately, during the occurrence of an electrostatic discharge event (which may be caused by the application of a voltage spike to the input/output pad), current localization may take place near the drain regions of the central MOS cells (shown as region 18) if their respective drain and source regions turn-on early in response to impact ionization breakdown at the reverse-biased drain region junction. In particular, in the event lateral current is established in the P-well region (underneath the NMOS cells) the potential of the P-well region adjacent the centrally-located source and drain regions will increase and cause an early turn-on of the forward-biased P-well/N-source junction. As will be understood by those skilled in the art, this early turn-on can cause a nonuniform electrostatic discharge current to be established in the NMOS cells and poor electrostatic discharge protection capability.
Thus, notwithstanding the recognition of the problem of electrostatic discharge and electrical overstress faults and the many attempts to inhibit integrated circuit failure resulting therefrom using conventional ESD/EOS protection circuits, there continues to be a need for improved electrostatic discharge protection devices.